Removing cell demultiplexing performance bottleneck in ATM pseudo wire emulation over MPLS networks

In this paper, a scheme is proposed to allow a large number of cells to be demultiplexed, without having to implement special ASIC-based hardware optimized for cell demultiplexing. The idea is to configure a sequence of concatenated data plane processing devices to share the cell demultiplexing task with the egress PE. Performance analysis shows that the use of just two processing devices is sufficient to achieve high transport efficiency. This may as well be achieved by the addition of one router without a central control card. Therefore, service providers can employ this scheme to enable cell multiplexing with limited add-on cost, while preserving the existing investment.